| Component |
Type |
Excerpt from Data Sheet |
Download |
| DATA SHEET |
adc equalizer |
CONVERSION ADC PLL EQUALIZER HALF NYQUIST CARRIER RECOVERYrate •Integrated adaptive equalizer (linear transversal equalizer or decision feedback equalizer |
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| MAX12553 DS |
adc equalizer |
and dif- ferential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer (DCE) ADC conversion results |
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| Multistandard TV Audio Processor and Digital Sound Demodulator |
adc equalizer |
Path (via ADC) Characteristics .89 11.9 MONOIN to ADC and I2S Output Path Characteristicsand Carrier Offset recovery ¦Smart Volume Control ¦5-band Equalizer |
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| MULTISTANDARD TV AUDIO PROCESSOR AND DIGITAL SOUND DEMODULATOR |
adc equalizer |
ADC) Characteristics .87 11.9 MONOIN to ADC and I2S Output Path Characteristicss Overmodulation and Carrier Offset recovery s Smart Volume Control s 5-band Equalizer |
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| OR51132 Demodulator OR51132 Simplified Block Diagram |
adc equalizer |
ADC RF AGC IF AGC 10-bit ADC NTSC Audio Core IIS Output NTSC AudioVSB Performance •Superior VSB multi-path rejection with adjustable –15.5 to +45.5 µs 576-tap equalizer |
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| Digital Reception/ Transmission IC Integrated DVB– compliant QAM Demodulator A.. |
adc equalizer |
Frequency) Fully Digital Carrier Recovery (Coherent or Differential for QPSK) Robust Equalizer Acquisition •Selectable Transversal or Decision Feedback Equalizer •Dual Phase |
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| HMS30C1100/1200 |
adc equalizer |
Description 1 ADCDGET O ADC Data Enable 2 ADCFLAG I ADC Data Ready 3 -10 ADCAD[0:7] I ADC Digital Data Input 11 VDDof Voice Recording/ Playback and Tone/Equalizer |
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| "Analog Interface Circuits" |
adc equalizer |
Range ADC and DAC D Variable ADC and DACChebyshev/elliptic transitional) low-pass and high-pass filters, respectively and a fourth-order equalizer |
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| MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY ADP.. |
adc equalizer |
LRCK1 BCKI Page 6 STA016T 6/45 14 SDI I ADC serial data From ADC 12 LRCKI I ADC left/right Clock From ADC PCM OUT interface 20 LRCKOvolume and tone equalizer |
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| AT76C651B Preliminary |
adc equalizer |
Os Pull-up Voltage Direction Analog In (IF) ADCCoherent or Differential for QPSK) Robust Equalizer Acquisition •Selectable Transversal or Decision Feedback Equalizer |
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| MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY ADP.. |
adc equalizer |
LRCK1 BCKI Page 6 STA016T 6/45 14 SDI I ADC serial data From ADC 12 LRCKI I ADC left/right Clock From ADC PCM OUT interface 20 LRCKOvolume and tone equalizer |
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| AD1985 AC 97 SoundMAX Codec Data Sheet (Rev. A) |
adc equalizer |
R ADC RATE PCM C/LFE DAC RATE PCM FRONT DAC RATE PCM SURR DAC RATE DAC SLOT LOGIC ADC SLOT LOGICFEATURES Integrated parametric equalizer (EQ) Stereo microphone with |
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| AD1981B AC '97 SoundMAX Codec Data Sheet (REV. A) |
adc equalizer |
ADC GA 16-BIT -ADC PCM FRONT DAC RATE M 16-BIT -ADC M 16-BIT -ADC PCM L/R ADC RATE RECORD SELECT OR V REF G V REFOUT LINE_IN_R CODEC CORE ADC AND DACDigital Equalizer |
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| MAX1206 DS |
adc equalizer |
variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer. The MAX1206 features parallel, CMOS-compatible out- puts. The digital output |
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| AD1980 AC 97 SoundMAX Codec Data Sheet (REV. 0) |
adc equalizer |
GA M M M M G =GAIN A =ATTENUATION M =MUTE Z =HIGH Z M G 16-BIT -ADC M G 16-BIT -ADC PCM L/R ADCLOSEL HPSEL HPSEL ENHANCED FEATURES Integrated Parametric Equalizer |
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| MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY |
adc equalizer |
ADC INPUT INTERFACE 8 27 25 SDI_ADC LRCK_ADC SCK_ADC SDO 9 10 11 12 SCKT LRCKT OCLK SYSTEMgoes through a software vol- ume control and a two-band equalizer |
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| AD1981B AC '97 SoundMAX Codec Data Sheet (Rev. C) |
adc equalizer |
CONTROL REGISTERS V REFOUT V REF B YPA SS 16-BIT S -ADC 16-BIT S -ADC 16-BIT S -ADC 16-BIT S -ADC 20-BIT S -DACMIC preamplifier support Built-in digital equalizer |
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| MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY |
adc equalizer |
ADC INPUT INTERFACE 8 27 25 SDI_ADC CRCK_ADC SCK_ADC SDO 9 10 11 12 SCKT LRCKT OCLK SYSTEMthrough a software vol- ume control and a two-band equalizer |
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| MAX1207 DS |
adc equalizer |
variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer. The MAX1207 features parallel, CMOS-compatible out- puts. The digital output |
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| MAX1127 DS |
adc equalizer |
to-digital converter (ADC) features fully differential inputs, a pipelined architecture, and digital error correction. This ADC is optimized for low-powercycle equalizer |
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